Physical Design Engineer

? 8-12 years of hands on experience, P&R from RTL to GDS including timing closure and Physical verification preferred but not required.
? Design experience in all aspects of physical design.
? Include all aspects of physical design including synthesis, floor planning, place and route,
Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
? Expert knowledge of Synopsys IC-Compiler and proficient and powerful user of Synopsys Tool Suite (DC/ICC/Star/PT).
? Technologies: 28nm and below.
? Experience in Mentor Calibre tools to run Physical verification and/or in ANSYS Redhawk to run IR-analysis is a Plus.
? Education: B.Tech/BE/ME/M.Tech
? Efficient communication skills to interface with Front End Design team to resolve Design Issues
? Experience in Tcl/Tk, PERL, Makefile is a Plus